In many modern systems containing integrated circuits (ICs), low power is critical. In order to obtain low power within a product, transistor switching must be reduced to a minimum. In order to reduce transistor switching to a minimum, a clock signal or multiple clock signals are isolated from the internal circuitry of integrated circuits to prevent transistors with the integrated circuits from changing logical state. In addition, external terminals or pins or the IC may be tri-stated or isolated to further reduce power by minimizing current drain due to voltage mismatch. A main problem with using this technique of stopping a clock and isolating external terminals is that verification and testing of this low power mode is nearly impossible. How does one test an integrated circuit to determine that a low power mode was entered, maintained and exited properly if, when in this mode, all terminals are isolated and a clock is not functional. With no clock and no terminals to access the part, no test data can be input to and read from the part to logically verify low power mode operation.
To remedy this problem, many ICs are tested using an expensive analog current measurement technique. When in low power mode, a part is to draw a low level of power (assume 30 microamperes for sake of example). A current measurement resulting in a reading of 100 microamperes drawn or even 30.00001 microamps may indicate a problem with the low power mode operation. Even thought this technique recognizes a problem, it has no way of aiding a designer or tester in determining where in the IC the problem lies. Therefore, the designer or testers must wade through millions of transistors to find the few or many transistors that are causing the low power problems after the current measurements find there is a problem. Due to the need for finding small increments in current, an expensive current measurement device is needed. This approach is therefore not overly useful.
In other cases, ICs have been built with on-chip test controllers that are never capable of entering into low power mode. Because the test controller never enters low power mode, the test controller can be used to test the rest of the IC when in a low power mode of operation. Unfortunately, a portion of an IC that is incapable of entering a low power mode of operation significantly reduces the part's ability to obtain a lowest possible low power mode of operation. Without a lowest-possible mode of low power, test controller current draw will result in hours or days of lost battery time in portable systems that require a minimum current draw for ICs. Therefore, a need exists for a way to test an IC, especially internal low power clock handling of a low power mode of operation within an IC during low power mode. In addition, a method is needed to verify that a low power mode can be properly entered and exited, and that low power mode circuitry does not interfere with normal mode operation.